1. Technical Field
The present invention relates to packaging electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. In particular, this invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning in bare chips under bias conditions so that chips with defects which could cause premature failure can be accelerated to failure, thereby avoiding incorporation of bad chips into a module.
2. Description of the Prior Art
One basic problem with existing technology is that chips which are available are not fully tested. This is due to a number of factors. First, the present manufacturing approach is to test chips at the wafer level just to the point that insures that the chip will probably work in the final package. At this point, chips are packaged and then fully tested. This manufacturing approach is economical for two reasons. First, it is necessary to test the packaged circuit in all cases because of the possibility of failure during the packaging operation. Packaging failures can occur as a failed package, a failure in the die to package wire bonding process or damage to the die during operations subsequent to wafer probing including sawing and placement of die into a package. Second, the number of bad die which pass wafer probe but which subsequently do not pass full testing is relatively small. As a result, the cost of packaging die before full test is not significant. Another reason chips are not fully tested at the wafer level is due to limited speed capability in wafer probing systems. Typically, probes are relatively long and are not impedance stabilized. As a result, as frequencies increase, crosstalk and ringing on digital lines exceeds the noise margin of the system and makes testing impossible. Special test fixtures have been built which allow testing of packaged parts at high speed.
A new problem which limits full testing at the wafer level is due to the number of I/O pads on a given chip. As chip complexity increases, the number of pads on the chip increases to a point where probing all the pads on the chip at one time becomes difficult or impossible. A further complicating factor is the trend toward decreasing the size of chip pads. As the pad size decreases, the ability of conventional probes to make contact to the pads is decreased. These two problems again require that some method other than wafer probing be used to completely test the chips.
High performance testing probes are becoming available based on thin film technology. A major problem with the high performance thin film probe, however, is that it is very expensive and requires a custom system for optimum utilization. Finally, thin film bump probes do not make good electrical connection through the oxide on conventional aluminum pads. The problem here then is to provide a method which allows so called bump probes to make good electrical connection in the face of conventional aluminum chip pads and to utilize a single optimized bump probe configuration for probing a variety of integrated circuit chips.
Techniques are available for making temporary interconnection to area arrays of pads which give a high density of interconnect and good electrical performance. These techniques, however, are amenable to probing of printed circuit boards and not to probing of IC chips. This is due primarily to the fact that IC chips are available with pads on their periphery and not with area arrays of pads. In addition, the aluminum pad material on the chip is subject to damage by this probing approach. The problem then is that area array contact means such as pogo sticks and button contacts cannot be used for high performance, high interconnect density probing of IC chips.
Another problem relates to the burn-in of bare chips. Burn-in is required to eliminate the early failure of IC chips in a module such that chips which are prone to fail early in their life cycle are not incorporated into a module. In order to accelerate failures of this variety, it is generally required that the chips be operated at a high temperature and under bias conditions with power applied to the chips. In many situations, it is also desirable to apply a rudimentary level of clocking signal to exercise the chip in some way while the burn-in is occurring. This has been done in conventional systems by first packaging the chip and then placing the package in a socket which is mounted on a printed circuit board. Pins of the socket are connected through resistors to power. Clock points on the chips are connected to a clock and power is applied to the chip. Typically, packaged parts are burned-in for as long as 300 hours where very high reliability levels are required, such as spacecraft applications. Burning-in chips at the wafer level is not feasible because there is no provision for bias connection or connection of power, ground and clock signals to all chips on the wafer. The problem then is to find a method wherein a plurality of bare chips can be burned-in under bias.
Several patents have recently issued relating to strategies for bare chip testing, see, for example, U.S. Pat. Nos. 4,884,122 and 4,866,508. These patents relate to methods and structure for bare chip tests and burn-in and, in particular, to specific structures for obtaining temporary interconnect to chips for the purpose of test and burn-in. The disclosed invention also relates to methods and structure for bare chip test and burn-in. It should be noted that the basic concept of making temporary interconnect to a device for the purpose of testing that device is not new. The methods and structure which are disclosed in this invention distinguish over the methods disclosed in the prior art in an important aspect in that there is no requirement for application and subsequent peeling of any overlay layer. Instead, the disclosed structure of the present invention employs a solvent sensitive encapsulant, which (as described herein) has several practical advantages over the overlay approach.